library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.FAW_TYPES.all;

entity RefSampledPointsShiftRegisterS is
    Port ( clk_rspsrs : in  STD_LOGIC;
           data_in_rspsrs : in  STD_LOGIC_VECTOR (7 downto 0);
           we_rspsrs : in  SR_ENABLE_ROWS;
           oe_rspsrs : in  SR_ENABLE_BUS;
			  oe_rspsrs_rows : in SR_ENABLE_ROWS;
           sclear_rspsrs : in  STD_LOGIC;
           data_out_rspsrs : out  RSPSRC_SR_DATA_BUS);
end RefSampledPointsShiftRegisterS;

architecture Archi of RefSampledPointsShiftRegisterS is

	component RSP_ShiftRegister is
		Port ( 
			  clk_rspsr : in  STD_LOGIC;
           data_in_rspsr : in  STD_LOGIC_VECTOR (7 downto 0);
			  we_rspsr : in std_logic;
           oe_rspsr : in STD_LOGIC_VECTOR (N_SP_IN_ROW-1 downto 0);
			  oe_rspsr_row : in STD_LOGIC;
           sclear_rspsr : in  STD_LOGIC;
			  data_out_rspsr : out  RSPSR_SR_DATA_BUS
			  );
	end component;

begin

	ShiftRegisters : for i in 0 to RSPSRC_SR_REGISTERS-1 generate
		ShiftRegister: RSP_ShiftRegister
		port map(
			clk_rspsr=>clk_rspsrs,
			data_in_rspsr=>data_in_rspsrs,
			we_rspsr=>we_rspsrs(i),
			oe_rspsr=>oe_rspsrs(i),
			oe_rspsr_row=>oe_rspsrs_rows(i),
			sclear_rspsr=>sclear_rspsrs,
			data_out_rspsr=>data_out_rspsrs(i)
		);
	end generate ShiftRegisters;


end Archi;

